As technology evolves into era of sub-micron, there is a desire to integrate various memory elements with high speed logic circuit elements into a single chip or an integrated circuit (IC) to form an embedded memory. For example, magnetic random access memory (MRAM) cells include magnetic tunnel junction (MTJ) elements, or stacks sandwiched between top and bottom electrodes, or terminals which are generally connected to interconnects in dielectric layers. During integration, the process windows and reliabilities of the MRAM cells may degrade due to process limitations.
For example, the formation of the electrical connection to the top of the MRAM cell includes forming a dielectric layer over the MRAM cell, smoothing the surface of that dielectric layer with planarization, etching a via through the dielectric layer, and then forming an interconnect within the open via. The process variation in the planarization and etching process is more than a dimension of the top layer of the MRAM cell. As a result, the interconnect extending to the top layer of the MRAM cell is not long enough in some cases such that a portion of the dielectric remains between the interconnect and the MRAM cell and the circuit is permanently open. In other instances, the interconnect is too long and passes through the top layer of the MRAM cell so the MRAM cell is permanently shorted. One option is to use middle etch stop layer (ESL) to cover the variations, however, this is not compatible with logic processing and has a much larger RC compared with scheme without ESL.
Accordingly, it is desirable to provide integrated circuits and methods of forming such integrated circuits with MRAM cells and interconnects where the interconnect reliably forms an electrical connection with the MRAM cell without shorting the MRAM cell and which is compatible with logic processing.